The present invention relates to a process for fabricating a semiconductor device having a multilevel interconnection.
With increasing demand for LSIs having a higher degree of integration, more multilevel interconnections are brought to use. Accordingly, the steps for fabricating interconnections are accounting for a larger part in the entire process for fabricating a semiconductor device. In a process for fabricating a 0.35-.mu.m ASIC (Application Specific IC) device, for instance, it is said that the process for fabricating the interconnection account for about one-third of the entire fabricating process.
Known processes for fabricating an interconnection heretofore comprise alternately stacking an interconnection layer and an insulating film on a substrate.
More specifically, referring to FIG. 7, a first interconnection 52 is formed on the surface of a substrate 50 with a first insulating film interposed therebetween. Then, a second interconnection 54 is formed on the first interconnection 52 with a second insulating film 53 interposed therebetween. Similarly, a third insulating film 56, a third interconnection 57, a fourth insulating film 58, and a fourth interconnection 59 are formed sequentially in this order to form a multilevel interconnection.
The multilevel interconnection described hereinbefore greatly contributes to the implementation of more compact chips having a yet improved performance.
However, in cases of forming a multilevel interconnection in accordance with a related art process described above, step height of the interconnections increases with the increasing number of interconnection layers. This makes the processing of the interconnection more difficult as the process proceeds to the steps related to the upper layers, and causes problems such as contact failure or short circuit and/or open circuit failure of the interconnections.
Referring to FIG. 7, for example, in the case where a contact hole 55 is provided to the first insulating film 51 and the second insulating film 53, the step height of the second interconnection becomes extremely large at the portion of the contact hole. It can be see that such a large step height disables the formation of a good contact between the second interconnection 54 and the third interconnection 56 formed in the upper portion of the second interconnection.
Such a contact failure or short circuit and/or open circuit failure of the interconnections lowers the product yield of semiconductor devices.